VMOV (between two general-purpose registers and a doubleword floating-point register)

Copy two general-purpose registers to or from a SIMD&FP register copies two words from two general-purpose registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword register in the Advanced SIMD and floating-point register file to two general-purpose registers.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

constant to_arm_registers = (op == '1'); constant t = UInt(Rt); constant t2 = UInt(Rt2); constant m = UInt(M:Vm); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 then UNPREDICTABLE; if to_arm_registers && t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If to_arm_registers && t == t2, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The value in the destination register is unknown.

T1

Decode for all variants of this encoding

constant to_arm_registers = (op == '1'); constant t = UInt(Rt); constant t2 = UInt(Rt2); constant m = UInt(M:Vm); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 then UNPREDICTABLE; if to_arm_registers && t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If to_arm_registers && t == t2, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The value in the destination register is unknown.

Assembler Symbols