VMOV (general-purpose register to scalar) -- AArch32

VMOV (general-purpose register to scalar)

Copy a general-purpose register to a vector element copies a byte, halfword, or word from a general-purpose register into an Advanced SIMD scalar.

On a Floating-point-only system, this instruction transfers one word to the upper or lower half of a double-precision floating-point register from a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.

For more information about scalars see Advanced SIMD scalars.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	1	1	0	0	opc1		0	Vd				Rt				1	0	1	1	D	opc2		1	(0)	(0)	(0)	(0)
cond

Encoding for the A1 variant

VMOV{<c>}{<q>}{.<size>} <Dd[x]>, <Rt>

Decode for this encoding

constant bits(4) opc = opc1:opc2; if opc == '0x10' then UNDEFINED; constant integer lsb = LowestSetBit(opc<0,3>); constant integer esize = 8 << lsb; constant integer index = UInt(opc<2:lsb>); constant boolean advsimd = (esize < 32); constant d = UInt(D:Vd); constant t = UInt(Rt); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	1	1	0	0	opc1		0	Vd				Rt				1	0	1	1	D	opc2		1	(0)	(0)	(0)	(0)

Encoding for the T1 variant

VMOV{<c>}{<q>}{.<size>} <Dd[x]>, <Rt>

Decode for this encoding

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

The data size. It must be one of:

8: Encoded as opc1<1> = 1. [x] is encoded in opc1<0>, opc2.
16: Encoded as opc1<1> = 0, opc2<0> = 1. [x] is encoded in opc1<0>, opc2<1>.
32: Encoded as opc1<1> = 0, opc2 = 0b00. [x] is encoded in opc1<0>.
omitted: Equivalent to 32.

<Dd[x]>

The scalar. The register <Dd> is encoded in D:Vd. For details of how [x] is encoded, see the description of <size>.

<Rt>	The source general-purpose register.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); Elem[D[d],index,esize] = R[t]<esize-1:0>;

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_32, pseudocode v2025-03_rel ; Build timestamp: 2025-03-21T16:47