Concatenate elements from four vectors
This instruction concatenates every fourth element from each of the four source vectors and places them in the corresponding elements of the four destination vectors.
This instruction is unpredicated.
It has encodings from 2 classes: 8-bit to 64-bit elements and 128-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 1 | 0 | |||||
| op | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); if size == '11' && MaxImplementedSVL() < 256 then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00');
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 1 | 0 | ||||
| op | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); if MaxImplementedSVL() < 512 then EndOfDecode(Decode_UNDEF); constant integer esize = 128; constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00');
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. |
| <T> |
Is the size specifier,
encoded in
|
| <Zd4> |
Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. |
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 4 then EndOfDecode(Decode_UNDEF); constant integer quads = VL DIV (esize * 4); bits(VL) result0; bits(VL) result1; bits(VL) result2; bits(VL) result3; for r = 0 to 3 constant bits(VL) operand = Z[n+r, VL]; constant integer base = r * quads; for q = 0 to quads-1 Elem[result0, base+q, esize] = Elem[operand, 4*q+0, esize]; Elem[result1, base+q, esize] = Elem[operand, 4*q+1, esize]; Elem[result2, base+q, esize] = Elem[operand, 4*q+2, esize]; Elem[result3, base+q, esize] = Elem[operand, 4*q+3, esize]; Z[d+0, VL] = result0; Z[d+1, VL] = result1; Z[d+2, VL] = result2; Z[d+3, VL] = result3;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2025-03_rel, pseudocode v2025-03_rel ; Build timestamp: 2025-03-21T17:41
Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.