The DLR characteristics are:
In Debug state, holds the address to restart from.
AArch32 System register DLR bits [31:0] are architecturally mapped to AArch64 System register DLR_EL0[31:0].
This register is present only when FEAT_AA32 is implemented. Otherwise, direct accesses to DLR are UNDEFINED.
DLR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | |||||||||||||||||||||||||||||||
Restart address.
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b011 | 0b0100 | 0b0101 | 0b001 |
if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else R[t] = DLR;
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b011 | 0b0100 | 0b0101 | 0b001 |
if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif !Halted() then UNDEFINED; else DLR = R[t];
21/03/2025 17:52; 154105dd5041532b480d9ef0c018b8420cbe5c19
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