DC CIPAE

This instruction is present only when FEAT_MEC is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to DC CIPAE are UNDEFINED.

Attributes

Field descriptions

NS, bit [63]
When FEAT_RME_GDI is implemented:

Together with the NSE2 and NSE field, this field specifies the target physical address space.

NSE2	NSE	NS	Meaning
0b0	0b0	0b0	Reserved.
0b0	0b0	0b1	Reserved.
0b0	0b1	0b0	Reserved.
0b0	0b1	0b1	Realm.
0b1	0b0	0b0	System Agent.
0b1	0b0	0b1	NS Protected.
0b1	0b1	0b0	Reserved.
0b1	0b1	0b1	Reserved.

If {NSE2, NSE, NS} is reserved, then no cache entries are required to be cleaned or invalidated.

Otherwise:

Together with the NSE field, this field specifies the target physical address space.

NSE	NS	Meaning
0b0	0b0	Reserved.
0b0	0b1	Reserved.
0b1	0b0	Reserved.
0b1	0b1	Realm.

If {NSE, NS} is not {1, 1}, then no cache entries are required to be cleaned or invalidated.

NSE, bit [62]

If FEAT_RME_GDI is implemented, this field together with the NS and NSE2 fields, specifies the target physical address space.

Otherwise, this field and the NS field specify the physical address space

For a description of the values derived by evaluating NS, NSE, and NSE2 together, see DC CIPAE.NS.

NSE2, bit [61]
When FEAT_RME_GDI is implemented:

Together with the NS and NSE field, this field specifies the target physical address space.

For a description of the values derived by evaluating NS and NSE together, see DC CIPAE.NS.

Otherwise:

Bits [60:56]

PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

Otherwise:

PA, bits [51:0]

Executing DC CIPAE

Accesses to this instruction use the following encodings in the System instruction encoding space:

DC CIPAE, <Xt>

op0	op1	CRn	CRm	op2
0b01	0b100	0b0111	0b1110	0b000

if !(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Realm) then UNDEFINED; else AArch64.DC(X[t, 64], CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE); elsif PSTATE.EL == EL3 then AArch64.DC(X[t, 64], CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE);

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NS	NSE	NSE2	RES0					PA[55:52]				PA
PA

DC CIPAE, Data or unified Cache line Clean and Invalidate by PA to PoE

Purpose

Configuration

Attributes

Field descriptions

NS, bit [63]
When FEAT_RME_GDI is implemented:

Otherwise:

NSE, bit [62]

NSE2, bit [61]
When FEAT_RME_GDI is implemented:

Otherwise:

Bits [60:56]

PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

Otherwise:

PA, bits [51:0]

Executing DC CIPAE

DC CIPAE, <Xt>

DC CIPAE, Data or unified Cache line Clean and Invalidate by PA to PoE

Purpose

Configuration

Attributes

Field descriptions

NS, bit [63]When FEAT_RME_GDI is implemented:

Otherwise:

NSE, bit [62]

NSE2, bit [61]When FEAT_RME_GDI is implemented:

Otherwise:

Bits [60:56]

PA[55:52], bits [55:52]When FEAT_D128 is implemented:

Otherwise:

PA, bits [51:0]

Executing DC CIPAE

DC CIPAE, <Xt>

NS, bit [63]
When FEAT_RME_GDI is implemented:

NSE2, bit [61]
When FEAT_RME_GDI is implemented:

PA[55:52], bits [55:52]
When FEAT_D128 is implemented: