The AMSCR characteristics are:
Control register for Secure, and Non-secure access to External AMU registers.
It is IMPLEMENTATION DEFINED whether AMSCR is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMU_EXTACR is implemented and FEAT_RME is not implemented. Otherwise, direct accesses to AMSCR are RES0.
AMSCR is a 64-bit register.
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| IMPL | RES0 | NSRA | RES0 | ||||||||||||||||||||||||||||
Reserved, RES0.
| IMPL | Meaning |
|---|---|
| 0b1 |
Indicates AMSCR is present. |
Access to this field is RAO/WI.
Reserved, RES0.
Register Access to all External Activity Monitors registers.
| NSRA | Meaning |
|---|---|
| 0b0 |
Non-secure access is disabled, RAZ/WI. |
| 0b1 |
Non-Secure access is enabled. |
Reserved, RES0.
Accesses to this register use the following encodings:
Accessible at offset 0xE40 from AMU
21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19
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