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ERRDEVARCH, Device Architecture Register

The ERRDEVARCH characteristics are:

Purpose

Provides discovery information for the component.

Configuration

ERRDEVARCH is implemented only as part of a memory-mapped group of error records.

Attributes

ERRDEVARCH is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
ARCHITECTPRESENTREVISIONARCHVERARCHPART

ARCHITECT, bits [31:21]

Defines the architect of the component. For RAS, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0b0100.

Bits [27:21] are the JEP106 identification code, 0b0111011.

Reads as 0b01000111011.

Access to this field is RO.

PRESENT, bit [20]

DEVARCH present. Indicates that the ERRDEVARCH register is present.

Reads as 0b1.

Access to this field is RO.

REVISION, bits [19:16]
When UInt(ERRDEVARCH.ARCHPART) == 0xA00 and ERRDEVARCH.ARCHVER == 0b0000:

Revision. Defines the architecture revision of the component.

The value of this field is an IMPLEMENTATION DEFINED choice of:

REVISIONMeaning
0b0000

RAS System Architecture, error record group v1.0.

0b0001

RAS System Architecture, error record group v1.1. As 0b0000 and also:

  • Simplifies ERR<n>STATUS.
  • Adds support for additional ERR<n>MISC<m> registers.
  • Adds support for the optional RAS Timestamp Extension.
  • Adds support for the optional Common Fault Injection Model Extension.

All other values are reserved.

Access to this field is RO.


When UInt(ERRDEVARCH.ARCHPART) == 0xA00 and ERRDEVARCH.ARCHVER == 0b0001:

Revision. Defines the architecture revision of the component.

REVISIONMeaning
0b0000

RAS System Architecture, error record group v2.0.

All other values are reserved.

Access to this field is RO.


When UInt(ERRDEVARCH.ARCHPART) == 0xA08 and ERRDEVARCH.ARCHVER == 0b0000:

Revision. Defines the architecture revision of the component.

REVISIONMeaning
0b0000

RAS System Architecture, fault injection group v1.0.

All other values are reserved.

Access to this field is RO.


Otherwise:

Reserved, RES0.

ARCHVER, bits [15:12]
When UInt(ERRDEVARCH.ARCHPART) == 0xA00:

Architecture Version. Defines the architecture version of the component.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ARCHVERMeaning
0b0000

RAS System Architecture, error record group v1.

0b0001

RAS System Architecture, error record group v2. As 0b0000 and also:

  • Adds an optional access control register, ERRACR.
  • Adds an optional control for disabling error counters.
  • Adds optional fault handling interrupt controls for Deferred errors.
  • Adds support for continuation and proxy error records.
  • Adds support for implementing Common Fault Injection Mechanism registers in a separate page from the error record registers.
  • Adds support for simple interrupt control registers.
  • Defines fields in ERRDEVID that describe these properties.

All other values are reserved.

ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHVER is ERRDEVARCH.ARCHID[15:12].

Access to this field is RO.


When UInt(ERRDEVARCH.ARCHPART) == 0xA08:

Architecture Version. Defines the architecture version of the component.

ARCHVERMeaning
0b0000

RAS System Architecture, fault injection group v1.

All other values are reserved.

ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHVER is ERRDEVARCH.ARCHID[15:12].

Access to this field is RO.


Otherwise:

Reserved, RES0.

ARCHPART, bits [11:0]

Architecture Part. Defines the architecture of the component.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ARCHPARTMeaning
0xA00

RAS System Architecture, error record group.

0xA08

RAS System Architecture, fault injection group.

ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHPART is ERRDEVARCH.ARCHID[11:0].

Access to this field is RO.

Accessing ERRDEVARCH

This section shows the offset of ERRDEVARCH when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRDEVARCH.

ERRDEVARCH can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xFBCERRDEVARCH

Accesses to this register are RO.

AArch32 Registers
AArch64 Registers
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Index by Encoding
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21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19

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