ERRIRQSR

This register is present only when interrupt configuration registers are implemented. Otherwise, direct accesses to ERRIRQSR are RES0.

Attributes

Field descriptions

When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts:

Bits [63:0]

Reserved, RES0.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers:

Bits [63:6]

CRIERR, bit [5]
When the Critical Error Interrupt is implemented:

Critical Error Interrupt Error.

CRIERR	Meaning
0b0	Critical Error Interrupt write has not returned an error since this field was last cleared to zero.
0b1	Critical Error Interrupt write has returned an error since this field was last cleared to zero.

The reset behavior of this field is:

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

Access to this field is W1C.

Otherwise:

CRI, bit [4]
When the Critical Error Interrupt is implemented:

Critical Error Interrupt write in progress.

CRI	Meaning
0b0	Critical Error Interrupt write not in progress.
0b1	Critical Error Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.

Otherwise:

ERIERR, bit [3]
When the Error Recovery Interrupt is implemented:

Error Recovery Interrupt Error.

ERIERR	Meaning
0b0	Error Recovery Interrupt write has not returned an error since this field was last cleared to zero.
0b1	Error Recovery Interrupt write has returned an error since this field was last cleared to zero.

The reset behavior of this field is:

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

Access to this field is W1C.

Otherwise:

ERI, bit [2]
When the Error Recovery Interrupt is implemented:

Error Recovery Interrupt write in progress.

ERI	Meaning
0b0	Error Recovery Interrupt write not in progress.
0b1	Error Recovery Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.

Otherwise:

FHIERR, bit [1]
When the Fault Handling Interrupt is implemented:

Fault Handling Interrupt Error.

FHIERR	Meaning
0b0	Fault Handling Interrupt write has not returned an error since this field was last cleared to zero.
0b1	Fault Handling Interrupt write has returned an error since this field was last cleared to zero.

The reset behavior of this field is:

On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

Access to this field is W1C.

Otherwise:

FHI, bit [0]
When the Fault Handling Interrupt is implemented:

Fault Handling Interrupt write in progress.

FHI	Meaning
0b0	Fault Handling Interrupt write not in progress.
0b1	Fault Handling Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

Note

This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.

Otherwise:

When the implementation does not use the recommended layout for the ERRIRQCR registers:

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing ERRIRQSR

If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRIRQSR are IMPLEMENTATION DEFINED.

This section shows the offset of ERRIRQSR when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRIRQSR.

ERRIRQSR can be accessed through the memory-mapped interfaces:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																										CRIERR	CRI	ERIERR	ERI	FHIERR	FHI

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

ERRIRQSR, Error Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts:

Bits [63:0]

When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers:

Bits [63:6]

CRIERR, bit [5]
When the Critical Error Interrupt is implemented:

Otherwise:

CRI, bit [4]
When the Critical Error Interrupt is implemented:

Otherwise:

ERIERR, bit [3]
When the Error Recovery Interrupt is implemented:

Otherwise:

ERI, bit [2]
When the Error Recovery Interrupt is implemented:

Otherwise:

FHIERR, bit [1]
When the Fault Handling Interrupt is implemented:

Otherwise:

FHI, bit [0]
When the Fault Handling Interrupt is implemented:

Otherwise:

When the implementation does not use the recommended layout for the ERRIRQCR registers:

IMPLEMENTATION DEFINED, bits [63:0]

Accessing ERRIRQSR

ERRIRQSR can be accessed through the memory-mapped interfaces:

ERRIRQSR, Error Interrupt Status Register

Purpose

Configuration

Attributes

Field descriptions

When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts:

Bits [63:0]

When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers:

Bits [63:6]

CRIERR, bit [5]When the Critical Error Interrupt is implemented:

Otherwise:

CRI, bit [4]When the Critical Error Interrupt is implemented:

Otherwise:

ERIERR, bit [3]When the Error Recovery Interrupt is implemented:

Otherwise:

ERI, bit [2]When the Error Recovery Interrupt is implemented:

Otherwise:

FHIERR, bit [1]When the Fault Handling Interrupt is implemented:

Otherwise:

FHI, bit [0]When the Fault Handling Interrupt is implemented:

Otherwise:

When the implementation does not use the recommended layout for the ERRIRQCR registers:

IMPLEMENTATION DEFINED, bits [63:0]

Accessing ERRIRQSR

ERRIRQSR can be accessed through the memory-mapped interfaces:

CRIERR, bit [5]
When the Critical Error Interrupt is implemented:

CRI, bit [4]
When the Critical Error Interrupt is implemented:

ERIERR, bit [3]
When the Error Recovery Interrupt is implemented:

ERI, bit [2]
When the Error Recovery Interrupt is implemented:

FHIERR, bit [1]
When the Fault Handling Interrupt is implemented:

FHI, bit [0]
When the Fault Handling Interrupt is implemented: