The GICR_ICACTIVER<n>E characteristics are:
Removes the active state from the corresponding PPI.
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_ICACTIVER<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ICACTIVER<n>E is a 32-bit register.
For the extended PPIs, removes the active state to interrupt number x. Reads and writes have the following behavior:
| Clear_active_bit<x> | Meaning |
|---|---|
| 0b0 | If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect. |
| 0b1 | If read, indicates that the corresponding interrupt is active, or is active and pending. If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect. |
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICACTIVER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
The effect of a write must be visible in finite time.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | SGI_base | 0x0380 + (4 * n) | GICR_ICACTIVER<n>E |
Accesses to this register are RW.
21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19
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