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GICR_ICPENDR0, Interrupt Clear-Pending Register 0

The GICR_ICPENDR0 characteristics are:

Purpose

Removes the pending state from the corresponding SGI or PPI.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_ICPENDR0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
Clear_pending_bit31Clear_pending_bit30Clear_pending_bit29Clear_pending_bit28Clear_pending_bit27Clear_pending_bit26Clear_pending_bit25Clear_pending_bit24Clear_pending_bit23Clear_pending_bit22Clear_pending_bit21Clear_pending_bit20Clear_pending_bit19Clear_pending_bit18Clear_pending_bit17Clear_pending_bit16Clear_pending_bit15Clear_pending_bit14Clear_pending_bit13Clear_pending_bit12Clear_pending_bit11Clear_pending_bit10Clear_pending_bit9Clear_pending_bit8Clear_pending_bit7Clear_pending_bit6Clear_pending_bit5Clear_pending_bit4Clear_pending_bit3Clear_pending_bit2Clear_pending_bit1Clear_pending_bit0

Clear_pending_bit<x>, bit [x], for x = 31 to 0

Removes the pending state from interrupt number x. Reads and writes have the following behavior:

Clear_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending.

If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:

  • If the interrupt is not pending and is not active and pending.
  • If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

The reset behavior of this field is:

Accessing GICR_ICPENDR0

When affinity routing is not enabled for the Security state of an interrupt in GICR_ICPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ICPENDR<n> with n=0.

This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ICENABLER<n>.

When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.

GICR_ICPENDR0 can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0280GICR_ICPENDR0

Accesses to this register are RW.

AArch32 Registers
AArch64 Registers
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21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19

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