GICR_ISACTIVER<n>E, Interrupt Set-Active Registers, n = 1 - 2

The GICR_ISACTIVER<n>E characteristics are:

Purpose

Adds the active state to the corresponding PPI.

Configuration

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_ISACTIVER<n>E are RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISACTIVER<n>E is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Set_active_bit31	Set_active_bit30	Set_active_bit29	Set_active_bit28	Set_active_bit27	Set_active_bit26	Set_active_bit25	Set_active_bit24	Set_active_bit23	Set_active_bit22	Set_active_bit21	Set_active_bit20	Set_active_bit19	Set_active_bit18	Set_active_bit17	Set_active_bit16	Set_active_bit15	Set_active_bit14	Set_active_bit13	Set_active_bit12	Set_active_bit11	Set_active_bit10	Set_active_bit9	Set_active_bit8	Set_active_bit7	Set_active_bit6	Set_active_bit5	Set_active_bit4	Set_active_bit3	Set_active_bit2	Set_active_bit1	Set_active_bit0

Set_active_bit<x>, bit [x], for x = 31 to 0

For the extended PPIs, adds the active state to interrupt number x. Reads and writes have the following behavior:

Set_active_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is active, or active and pending on this PE. If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect. After a write of 1 to this bit, a subsequent read of this bit returns 1.

Set_active_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or active and pending on this PE.

If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

On a GIC reset, this field resets to '0'.

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICR_ISACTIVER<n>E number, n, is given by n = (m-1024) DIV 32.
The offset of the required GICR_ISACTIVER<n>E is (0x200 + (4*n)).
The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

Accessing GICR_ISACTIVER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISACTIVER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

The effect of a write must be visible in finite time. Reading back the written value from either the Set-Active or Clear-Active registers guarantees that a deactivate from a CPU interface Ordered-after the read, will observe the effects of the write on the Active state of the interrupt.

GICR_ISACTIVER<n>E can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Redistributor	SGI_base	0x0300 + (4 * n)	GICR_ISACTIVER<n>E

Accesses to this register are RW.

21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19