TRBPIDR7, Peripheral Identification Register 7

The TRBPIDR7 characteristics are:

Purpose

Provides discovery information about the component.

For additional information, see the CoreSight Architecture Specification.

Configuration

TRBPIDR7 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPIDR7 are RES0.

Attributes

TRBPIDR7 is a 32-bit register.

Field descriptions

Bits [31:0]

Accessing TRBPIDR7

TRBPIDR7 can be accessed through the external debug interface:

Accessible as follows:

• When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
• Otherwise, accesses to this register are RO.

21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.