The TRCPIDR4 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCPIDR4 are RES0.
TRCPIDR4 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
Size of the component.
The value of this field is an IMPLEMENTATION DEFINED choice of:
SIZE | Meaning |
---|---|
0b0000 | One of the following is true:
|
0b0001..0b1111 |
The component occupies 2TRCPIDR4.SIZE 4KB blocks. |
Using this field to indicate the size of the component is deprecated. This field might not correctly indicate the size of the component. Arm recommends that software determine the size of the component from the Unique Component Identifier fields, and other IMPLEMENTATION DEFINED registers in the component.
This field has the value 0b0000.
Access to this field is RO.
Designer, JEP106 continuation code.
JEP106 identification and continuation codes, which are stored as follows:
These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
A JEDEC code takes the following form:
The parity bit in the JEP106 identification code is not included.
For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFD0 | TRCPIDR4 |
Accessible as follows:
21/03/2025 17:53; 154105dd5041532b480d9ef0c018b8420cbe5c19
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